This section is intended to introduce the reader to various aspects of art, which may be related to various aspects of the present invention that are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
A packet-oriented protocol parser also known as “packet parser” or “packet filter” searches in a header of a packet for specific fields e.g., a MAC address, an IP address or a specific port. Fast packet parsers are essential for applications like interfaces, switchers, routers or firewalls. These parsers are often implemented in hardware especially when it is required to recognize those specific fields in high data rate environments.
Transmission according to packet oriented protocols are performed in bursts, so that well known parsers architecture uses FIFOs to store incoming frames and to parse their headers offline, during the pause of a transmission. FIFO is an acronym for “First In, First Out”, which is an abstraction in ways of organizing and manipulation of data relative to time and prioritization. The term “FIFOs” refers to the way data stored in a queue is processed and also is used commonly in electronic circuits for buffering and flow control.
In general, it is not required that the parser has to process the packets in real-time. However, if a lot of different data streams have to be processed, large FIFOs are necessary to avoid a transmission interruption or possible frame errors.
In the State of the Art, implementations of packet parsers based on Field-Programmable Gate Arrays (FPGAs) are well-known. The following document contains an illustrative example of such a packet parser: “An Overview of Multiple CAM Designs in Virtex Family Devices”, J.-L. Brelet, Xilinx, Application Note (XAPP201), Sep. 23, 1999, found on http://www.xilinx.com/bvdocs/appnotes/xapp201.pdf.
But, in case of application requiring high throughput, like in a 10 Gigabit Ethernet interface, parsing of incoming frames has to be performed necessarily on the fly: in this case, the use of FIFOs is not adapted.
One of the goals of the present invention consists in analyzing in real-time packet-oriented protocol transmissions realized at fixed data rate without any FIFOs, which lead to additional latencies.
This invention deals with a reconfigurable and fast implementation of real-time streaming parser mapped onto a specific hardware architecture based on configurable cells like for example so called ‘Content Addressable Memories’ (also known under the acronym CAM) and registers, the invention is closely linked with a classification of the protocol fields.
One typical application for this invention is a reconfigurable filter for packet-oriented protocols in fast routers, switches and firewalls.